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Editing example 1: Technical paper abstract (excerpt)


This is an example of a good draft written by a non-native
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.


Original text [171 words]

A phase-locked loop (PLL) is used in a wide range of fields, such as the extraction of timing waveforms in digital communication and as the clock sources and frequency synthesizers in various systems. Accompanying the demands for a smaller size, high reliability, and economical efficiency of various equipment over the past few years, it has been required that the PLL is set in system LSI [1]-[3]. Therefore, all digital PLLs (ADPLL) based on various earlier schemes have been reported. The main characteristics necessary for this PLL are low jitter, wide lock-in range, and fast pull-in time. However, the ADPLL, which has the conventional basic structure, divides the fixed clock by a constant ratio and controls the phase by adding or erasing the standard clock pulses (fixed clock pulses), so there were some problems in which the lock-in range is very narrow and the pull-in time is very long in a conventional ADPLL. Various schemes have been proposed to solve this problem, but none provide significant improvements in the lock-in rage [4]-[6].





Edited text [129 words]

A phase-locked loop (PLL) has many uses, including extracting timing waveforms in digital communication and as a clock source and frequency synthesizer in various systems. To meet the continuing demands for small size, high reliability, and economic efficiency, PLLs have been set in system LSI [1]-[3], and various schemes for all-digital PLLs (ADPLL) have been reported. The main requirements that ADPLLs must meet are low jitter, wide lock-in range, and fast pull-in time. However, because conventional ADPLLs divide the fixed clock by a constant ratio and control the phase by adding or subtracting clock pulses, their lock-in range is narrow and their pull-in time is long. Various schemes have been proposed to solve these problems, but none has improved the lock-in range significantly [4]-[6].

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